Fast RTL Fault Simulation Using Decision Diagrams and Bitwise Set Operations

Author:

Reinsalu Uljana,Raik Jaan,Ubar Raimund,Ellervee Peeter

Publisher

IEEE

Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. In-Memory Fault as Address Simulation;2023 IEEE East-West Design & Test Symposium (EWDTS);2023-09-22

2. VECTOR-LOGICAL FAULT SIMULATION;Radio Electronics, Computer Science, Control;2023-06-29

3. Vector–Logic Synthesis of Deductive Matrices for Fault Simulation;Èlektronnoe modelirovanie;2023-04-24

4. Vector-deductive Memory-based Transactions for Fault-as-address Simulation;Èlektronnoe modelirovanie;2023-03-16

5. Vector-Deductive Memory-Based Transactions for Fault-As-Address Simulation;2022 12th International Conference on Dependable Systems, Services and Technologies (DESSERT);2022-12-09

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