In-Memory Fault as Address Simulation-Reference-Cited by-同舟云学术

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In-Memory Fault as Address Simulation

Published:2023-09-22 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE East-West Design & Test Symposium (EWDTS)
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Author:

Gharibi Wajeb¹,Chumachenko Svetlana²,Miroshnyk Maryna³,Abashidze Marina⁴,Litvinova Eugenia²,Kulak Georgiy⁵,Hahanov Vladimir²,Mishchenko Alexander

Affiliation:

1. University of Missouri-Kansas City,Kansas City,United States

2. Kharkov National University of Radioelectronics,Design Automation Department,Kharkov,Ukraine

3. V. N. Karazin Kharkiv National University,Kharkov,Ukraine

4. Batumi Maritime Academy,Maritime Faculty,Batumi,Georgia

5. Kharkov National University of Radio Electronics,Design Automation Department,Kharkov,Ukraine

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10296971/10297023/10297038.pdf?arnumber=10297038

Reference28 articles.

1. Vector-deductive Memory-based Transactions for Fault-as-address Simulation

2. Qubit-driven Fault Simulation

3. Quantum Models and Method for Analysis and Testing Computing Systems

4. Vector-Qubit models for SoC Logic-Structure Testing and Fault Simulation

5. Deductive qubit fault simulation

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