Optimizing CNN Computation Using RISC-V Custom Instruction Sets for Edge Platforms-Reference-Cited by-同舟云学术

Optimizing CNN Computation Using RISC-V Custom Instruction Sets for Edge Platforms

Published:2024-05 Issue:5 Volume:73 Page:1371-1384
ISSN:0018-9340
Container-title:IEEE Transactions on Computers
language:
Short-container-title:IEEE Trans. Comput.

Author:

Wang Shihang¹^ORCID,Wang Xingbo¹^ORCID,Xu Zhiyuan¹^ORCID,Chen Bingzhen¹^ORCID,Feng Chenxi¹^ORCID,Wang Qi²^ORCID,Ye Terry Tao³^ORCID

Affiliation:

1. Department of Electrical and Electronic Engineering, Southern University of Science and Technology, Shenzhen, China

2. Department of Electrical and Computer Engineering, The University of British Columbia, Vancouver, BC, Canada

3. Institute of Nanoscience and Applications (INA) and the Department of Electrical and Electronic Engineering, Southern University of Science and Technology, Shenzhen, China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/12/10494819/10420491.pdf?arnumber=10420491

Reference23 articles.

1. Implementation and Extension of Bit Manipulation Instruction on RISC-V Architecture using FPGA

2. Oolong: A Baseband processor extension to the RISC-V ISA

3. VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture

4. Customized Instructions for Protection Against Memory Integrity Attacks

5. ISA Extensions for Finite Field Arithmetic

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