Race logic architecture (RALA): a novel logic concept using the race scheme of input variables

Author:

Se-Joong Lee ,Hoi-Jun Yoo

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Star Network of Bipolar Memristive Devices Enables Sensing and Temporal Computing;Sensors;2024-01-14

2. Sense Amplifier Half-Buffer (SAHB): A Low-Power High-Performance Asynchronous Logic QDI Cell Template;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2016

3. Bitwise Competition Logic for compact digital comparator;2007 IEEE Asian Solid-State Circuits Conference;2007-11

4. The CMOS Carry-Forward Adders;IEEE Journal of Solid-State Circuits;2004-02

5. Analysis of High-Speed Logic Families;Lecture Notes in Computer Science;2003

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