Analysis of High-Speed Logic Families
Author:
Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/978-3-540-39762-5_2
Reference10 articles.
1. Bernstein, K., Carrig, K.M., Durham, C.M., Hansen, P.R., Hogenmiller, D., Nowak, E.J., Rohrer, N.J.: High Speed CMOS Design Styles. Kluwer Academic Publishers, Dordrecht (1999)
2. Woo, A.K.: Static PLA or ROM Circuit with Self-Generated Precharge. U.S. Patent # 4, 728, 827 (March 1, 1988)
3. Hwang, W., Gristede, G.D., Sanda, P., Wang, S.Y., Heidel, D.F.: Implementation of a Self-Resetting CMOS 64-Bit Parallel Adder with Enhanced Testability. IEEE Journal of Solid-State Circuits 34(8) (August 1999)
4. Allam, M.W., Elmasry, M.I.: Dynamic Current Mode Logic (DyCML): A New Low- Power High-Performance Logic Style. IEEE Journal of Solid-State Circuits 36(3) (March 2001)
5. Somasekhar, D., Roy, K.: Differential Current Switch Logic: A Low Power DCVS Logic Family. IEEE Journal of Solid-State Circuits 31(7) (July 1996)
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