Performance Analysis of a New Low Power BIST Technique in VLSI Circuit by Reducing the Input Vectors-Reference-Cited by-同舟云学术

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Performance Analysis of a New Low Power BIST Technique in VLSI Circuit by Reducing the Input Vectors

Published:2023-12-07 Issue: Volume:3 Page:1-5
ISSN:
Container-title:2023 6th International Conference on Electrical Information and Communication Technology (EICT)
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Author:

Kabir S. M Kifayat¹,Motalib Raihan²,Javed Fakrul Islam³,Ganguly Chamak⁴,Rakib Saeed Hossen⁵,Biswas Satyendra N.⁶

Affiliation:

1. ULKASEMI Pvt. Limited,Circuit and System Design,Dhaka,Bangladesh

2. ULKASEMI Pvt. Limited,IC Physical Design,Dhaka,Bangladesh

3. PrimeSilicon Technology (BD) Ltd,ASIC Physical Design,Dhaka,Bangladesh

4. Primeasia University,Electrical and Electronic Engineering,Dhaka,Bangladesh

5. Neural Semiconductor Ltd,Physical Design,Dhaka,Bangladesh

6. Bloomsburg University,Dept. of BiCEP,PA,USA,17815

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10426791/10427566/10427977.pdf?arnumber=10427977

Reference14 articles.

1. Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells

2. An Input Vector Monitoring Concurrent BIST Architecture Based on a Precomputed Test Set

3. Exploration of Various Test Pattern Generators for Power Reduction in LBIST

4. Low-Power Programmable PRPG With Test Compression Capabilities

5. Design and Implementation of Built in Self Test (BIST) forVLSI Circuits using Verilog;John;INTERNATIONAL JOURNAL OF ENGINEERING RESEARCH & TECHNOLOGY (IJERT) NCETET,2015

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