Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells-Reference-Cited by-同舟云学术

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Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells

Published:2014-07 Issue:7 Volume:22 Page:1625-1629
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Voyiatzis Ioannis,Efstathiou Costas

Funder

European Union and Greek national funds

Research Funding Program: Archimedes III

Investing in Knowledge Society through the European Social Fund

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/6841655/06589193.pdf?arnumber=6589193

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Performance Analysis of a New Low Power BIST Technique in VLSI Circuit by Reducing the Input Vectors;2023 6th International Conference on Electrical Information and Communication Technology (EICT);2023-12-07

2. A Tunable Concurrent BIST Design Based on Reconfigurable LFSR;Journal of Electronic Testing;2023-03-06

3. A Low-cost BIST Design Supporting Offline and Online Tests;Journal of Electronic Testing;2022-02

4. Development of an IoT seismograph;24th Pan-Hellenic Conference on Informatics;2020-11-20

5. A survey of fault detection and identification methods for Photovoltaic systems based on I-V curves;24th Pan-Hellenic Conference on Informatics;2020-11-20

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