Author:
Liu Cheng,Zhang Lei,Han Yinhe,Li Xiaowei
Cited by
43 articles.
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1. Congestion-Aware Vertical Link Placement and Application Mapping Onto 3-D Network-on-Chip Architectures;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-08
2. RLARA: A TSV-Aware Reinforcement Learning Assisted Fault-Tolerant Routing Algorithm for 3D Network-on-Chip;Electronics;2023-12-02
3. Fault-Tolerant Network-On-Chip;Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design;2023
4. Introduction;Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design;2023
5. Effective Routing Algorithm for Thermal Management in Vertically-
Partially-Connected 3D-network on Chip;Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering);2022-12