Block-level 3D IC design with through-silicon-via planning
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx5/6156603/6164924/06164969.pdf?arnumber=6164969
Cited by 18 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Comprehensive Physical Design Flow Incorporating 3-D Connections for Monolithic 3-D ICs;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-07
2. Construction of All Multilayer Monolithic RSMTs and Its Application to Monolithic 3D IC Routing;ACM Transactions on Design Automation of Electronic Systems;2023-12-18
3. TREAD-M3D: Temperature-Aware DNN Accelerators for Monolithic 3-D Mobile Systems;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-12
4. ATT-TA: A Cooperative Multiagent Deep Reinforcement Learning Approach for TSV Assignment in 3-D ICs;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-12
5. Construction of All Multilayer Monolithic Rectilinear Steiner Minimum Trees on the 3D Hanan Grid for Monolithic 3D IC Routing;Proceedings of the 2019 International Symposium on Physical Design;2019-04-04
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