Construction of All Multilayer Monolithic Rectilinear Steiner Minimum Trees on the 3D Hanan Grid for Monolithic 3D IC Routing
Author:
Affiliation:
1. Washington State University, Pullman, WA, USA
2. Washington State University, Washington State University, WA, USA
Funder
Defense Advanced Research Projects Agency
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3299902.3309749
Reference11 articles.
1. A legalization algorithm for multi-tier gate-level monolithic three-dimensional integrated circuits
2. FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design
3. Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout
4. Block-level 3D IC design with through-silicon-via planning
5. Compact-2D
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