Author:
Ewetz Rickard,Koh Cheng-Kok
Cited by
5 articles.
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1. Enhancing Static Timing Analysis Efficiency for RISC-V Processors Through Optimization Techniques;Lecture Notes on Multidisciplinary Industrial Engineering;2024
2. Scalable Construction of Clock Trees With Useful Skew and High Timing Quality;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2019-06
3. A Clock Tree Optimization Framework with Predictable Timing Quality;Proceedings of the 54th Annual Design Automation Conference 2017;2017-06-18
4. Clock Tree Construction based on Arrival Time Constraints;Proceedings of the 2017 ACM on International Symposium on Physical Design;2017-03-19
5. Construction of Latency-Bounded Clock Trees;Proceedings of the 2016 on International Symposium on Physical Design;2016-04-03