Scalable dual-instruction multiple-data processing on an efficient systolic-array architecture-Reference-Cited by-同舟云学术

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Scalable dual-instruction multiple-data processing on an efficient systolic-array architecture

Published:2024-05-27 Issue: Volume: Page:1-1
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Container-title:2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
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Author:

Tan Yuxi¹,Abdelhamid Riadh Ben²,Guo BingJie¹,Gao Qixiang¹,Nishimura Masaru¹,Yamaguchi Yoshiki³

Affiliation:

1. Graduate School of Science and Technology, University of Tsukuba,Ibaraki,Japan,305-8573

2. Institut für Technische Informatik, Universität Heidelberg,Heidelberg,Germany,69120

3. Institute of Systems and Information Engineering, University of Tsukuba,Ibaraki,Japan,305-8573

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10596331/10596332/10596443.pdf?arnumber=10596443

Reference8 articles.

1. Simultaneous branch and warp interweaving for sustained GPU performance

2. The dual-path execution model for efficient GPU control flow

3. A scalable multi-path microarchitecture for efficient GPU control flow

4. A radix-2 FFT algorithm for modern single instruction multiple data (SIMD) architectures

5. FPGA HPC using OpenCL

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