1. Systolic Array-Based Many-Core Processor with Simultaneous Dual-Instruction Issuance;14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART'24));2024-06-19
2. Scalable dual-instruction multiple-data processing on an efficient systolic-array architecture;2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW);2024-05-27
3. Pathfinding Future PIM Architectures by Demystifying a Commercial PIM Technology;2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2024-03-02
4. MIMD Programs Execution Support on SIMD Machines: A Holistic Survey;IEEE Access;2024
5. Grape: Practical and Efficient Graphed Execution for Dynamic Deep Neural Networks on GPUs;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28