Systolic Array-Based Many-Core Processor with Simultaneous Dual-Instruction Issuance

Author:

Tan Yuxi1ORCID,Nishimura Masaru1ORCID,Abdelhamid Riadh Ben2ORCID,Guo Bingjie1ORCID,Gao Qixiang1ORCID,Yamaguchi Yoshiki3ORCID

Affiliation:

1. Graduate School of Science and Technology, University of Tsukuba, Japan

2. The Institute for Computer Engineering, Heidelberg University, Germany

3. Institute of Systems and Information Engineering, University of Tsukuba, Japan and Research and Education Institute for Semiconductors and Informatics, Kumamoto University, Japan

Funder

JSPS KAKENHI (Grant-in-Aid for Scientific Research)

Publisher

ACM

Reference18 articles.

1. FGPU

2. Kevin Andryc, Tedy Thomas, and Russell Tessier. 2016. Soft GPGPUs for Embedded FPGAs: An Architectural Evaluation. In the 2nd International Workshop on Overlay Architectures for FPGAs (OLAF)(FPGA ’16). arxiv, Ithaca, NY, USA, 25–30. arxiv:1606.06454 [cs.AR] https://arxiv.org/html/1605.08149

3. Andy Glew. 2009. Coherent Threading. Berkeley ParLab seminar: [Online] https://parlab.eecs.berkeley.edu/sites/all/parlab/files/20090827-glew-vector.pdf. (accessed on Feb 5, 2024).

4. Performance Optimization of the HPCG Benchmark on the Sunway TaihuLight Supercomputer

5. Department of Economic and Social Affairs United Nations. 2015. Sustainable Development. [Online] https://sdgs.un.org/goals. (accessed on Feb 5 2024).

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