Sub-0.2 pJ/Access Schmitt Trigger Based 1-kb 8T SRAM Implemented Using 40-nm CMOS Process-Reference-Cited by-同舟云学术

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Sub-0.2 pJ/Access Schmitt Trigger Based 1-kb 8T SRAM Implemented Using 40-nm CMOS Process

Published:2022-09-21 Issue: Volume: Page:
ISSN:
Container-title:2022 International Conference on IC Design and Technology (ICICDT)
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Author:

Reddy Shiva¹,Sangalang Ralph Gerard B.¹,Wang Chua-Chin¹

Affiliation:

1. National Sun Yat-Sen University,Department of Electrical Engineering,Kaohsiung,Taiwan,80424

Funder

Ministry of Science and Technology

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9933043/9933065/09933116.pdf?arnumber=9933116

Reference10 articles.

1. Characterization of high speed 9T SRAM cell with enhanced data stability

2. A sub-threshold eight transistor (8T) SRAM cell design for stability improvement

3. 200-MHz Single-Ended 6T 1-kb SRAM With 0.2313 pJ Energy/Access Using 40-nm CMOS Logic Process

4. CMOS

5. A Novel 10T SRAM cell for Low Power Applications

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-10

2. Schmitt-Trigger-Based Low Power SRAM Implemented Using 45-nm CMOS Technology;2023 IEEE Region 10 Symposium (TENSYMP);2023-09-06

3. A 1.0 fJ energy/bit single‐ended 1 kb 6T SRAM implemented using 40 nm CMOS process;IET Circuits, Devices & Systems;2023-01-10

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