200-MHz Single-Ended 6T 1-kb SRAM With 0.2313 pJ Energy/Access Using 40-nm CMOS Logic Process
Author:
Funder
Taiwan MOST
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/9524868/09464247.pdf?arnumber=9464247
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Design of Highly Reliable 14T and 16T SRAM Cells Combined With Layout Harden Technique;IEEE Transactions on Device and Materials Reliability;2024-09
2. An in-Array Build-In Self-Test Scheme for Embedded SRAM Array;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-08
3. A 1-kb Sub-1 fJ/b Per Access CAM Design Using 40-nm CMOS Process;2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS);2023-11-19
4. A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-10
5. A 1.0 fJ energy/bit single‐ended 1 kb 6T SRAM implemented using 40 nm CMOS process;IET Circuits, Devices & Systems;2023-01-10
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