Test pattern generation for signal integrity faults on long interconnects-Reference-Cited by-同舟云学术

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Test pattern generation for signal integrity faults on long interconnects

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Container-title:Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)
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Author:

Attarha A.,Nourani M.

Publisher

IEEE Comput. Soc

Link

http://xplorestaging.ieee.org/ielx5/7901/21789/01011162.pdf?arnumber=1011162

Cited by 17 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A fully parallel BIST-based method to test the crosstalk defects on the inter-switch links in NOC;Microelectronics Journal;2013-03

2. TESTING OF SOC INTERCONNECTS USING EXTENDED IEEE 1500 STANDARD;Journal of Circuits, Systems and Computers;2012-08

3. BIST for network on chip communication infrastructure based on combination of extended IEEE 1149.1 and IEEE 1500 standards;Microelectronics Journal;2011-05

4. Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2010-02

5. A High-Level Signal Integrity Fault Model and Test Methodology for Long On-Chip Interconnections;2009 27th IEEE VLSI Test Symposium;2009-05

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