Improving Realistic Worst-Case Performance of NVCiM DNN Accelerators Through Training with Right-Censored Gaussian Noise-Reference-Cited by-同舟云学术

Improving Realistic Worst-Case Performance of NVCiM DNN Accelerators Through Training with Right-Censored Gaussian Noise

Published:2023-10-28 Issue: Volume: Page:
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Container-title:2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)
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Author:

Yan Zheyu¹,Qin Yifan¹,Wen Wujie²,Hu Xiaobo Sharon¹,Shi Yiyu¹

Affiliation:

1. Uuiversity of Notre Dame

2. North Carolina State University

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10323590/10323543/10323830.pdf?arnumber=10323830

Reference30 articles.

1. Computing-In-Memory Neural Network Accelerators for Safety-Critical Systems

2. Tolerating Noise Effects in Processing‐in‐Memory Systems for Neural Networks: A Hardware–Software Codesign Perspective

3. A Fault-Tolerant Neural Network Architecture

4. Making Memristive Neural Network Accelerators Reliable

5. Beol compatible dual-gate ultra thin-body w-doped indium-oxide transistor with ion=370?a/?m, ss= 73mv/dec and ion/ioff ratio¿ 4 × 109;chakraborty;2020 IEEE Symposium on VLSI Technology,2020

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