Author:
Feinberg Ben,Wang Shibo,Ipek Engin
Cited by
93 articles.
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1. Compute-in-Memory-Based Neural Network Accelerators for Safety-Critical Systems: Worst-Case Scenarios and Protections;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-08
2. On Error Correction for Nonvolatile Processing-In-Memory;2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA);2024-06-29
3. U-SWIM: Universal Selective Write-Verify for Computing-in-Memory Neural Accelerators;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-06
4. Harmonica: Hybrid Accelerator to Overcome Imperfections of Mixed-signal DNN Accelerators;2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS);2024-05-27
5. Error Detection and Correction Codes for Safe In-Memory Computations;2024 IEEE European Test Symposium (ETS);2024-05-20