An Open-Source Constraints-Driven General Partitioning Multi-Tool for VLSI Physical Design

Author:

Bustany Ismail1,Gasparyan Grigor1,Kahng Andrew B.2,Koutis Ioannis3,Pramanik Bodhisatta2,Wang Zhiang2

Affiliation:

1. Advanced Micro Devices,San Jose,CA,USA

2. University of California San Diego,La Jolla,CA,USA

3. New Jersey Institute of Technology,Newark,NJ,USA

Funder

NSF

Publisher

IEEE

Reference40 articles.

1. A linear-time heuristic for improving network partitions;fiduccia;Proc DAC,0

2. An Integrated Circuit Partitioning and TDM Assignment Optimization Framework for Multi-FPGA Systems

3. Multi-way system partitioning into a single type or multiple types of FPGAs;huang;Proc FPGA,0

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1. A Recursive Partitioning Approach to Improving Hypergraph Partitioning;2024 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE);2024-08-06

2. TBPart: An Effective Topological Order Balanced Hypergraph Partitioning Algorithm for VLSI Processor-based Hardware Emulation;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10

3. Solvers, Engines, Tools and Flows: The Next Wave for AI/ML in Physical Design;Proceedings of the 2024 International Symposium on Physical Design;2024-03-12

4. Invited Paper: IEEE CEDA DATC Emerging Foundations in IC Physical Design and MLCAD Research;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

5. PROBE3.0: A Systematic Framework for Design-Technology Pathfinding With Improved Design Enablement;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023

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