1. Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems
2. S.-H. Liou S. Liu R. Sun and H.-M. Chen "Timing driven partition for multi-fpga systems with tdm awareness " in Proceedings of the 2020 International Symposium on Physical Design pp. 111--118 2020. S.-H. Liou S. Liu R. Sun and H.-M. Chen "Timing driven partition for multi-fpga systems with tdm awareness " in Proceedings of the 2020 International Symposium on Physical Design pp. 111--118 2020.
3. M. Inagi , Y. Takashima , and Y. Nakamura , " Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems," in Field Programmable Logic and Applications, 2009 . FPL 2009. International Conference on , pp. 212 -- 217 , IEEE, 2009 . M. Inagi, Y. Takashima, and Y. Nakamura, "Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems," in Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on, pp. 212--217, IEEE, 2009.
4. W. N. Hung and R. Sun , " Challenges in large fpga-based logic emulation systems," in Proceedings of the 2018 International Symposium on Physical Design, pp. 26--33 , ACM , 2018 . W. N. Hung and R. Sun, "Challenges in large fpga-based logic emulation systems," in Proceedings of the 2018 International Symposium on Physical Design, pp. 26--33, ACM, 2018.
5. L. Cheng , D. Chen , M. D. Wong , M. Hutton , and J. Govig , " Timing constraint-driven technology mapping for fpgas considering false paths and multi-clock domains," in 2007 IEEE/ACM International Conference on Computer-Aided Design , pp. 370 -- 375 , IEEE , 2007 . L. Cheng, D. Chen, M. D. Wong, M. Hutton, and J. Govig, "Timing constraint-driven technology mapping for fpgas considering false paths and multi-clock domains," in 2007 IEEE/ACM International Conference on Computer-Aided Design, pp. 370--375, IEEE, 2007.