Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams-Reference-Cited by-同舟云学术

Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams

Published:2023-04 Issue:4 Volume:42 Page:1365-1378
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Kumar Jitendra¹^ORCID,Miyasaka Yukio²^ORCID,Srivastava Asutosh¹,Fujita Masahiro³^ORCID

Affiliation:

1. Department of Computer and Systems Science, Jawaharlal Nehru University, New Delhi, India

2. Department of Electrical Engineering and Computer Science, University of California at Berkeley, Berkeley, CA, USA

3. VLSI Design and Education Center, University of Tokyo, Tokyo, Japan

Funder

Department of Science and Technology (DST), India

Japan’s Society for the Promotion of Science

Council of Scientific & Industrial Research

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

Reference26 articles.

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