Verification of gate-level arithmetic circuits by function extraction-Reference-Cited by-同舟云学术

Verification of gate-level arithmetic circuits by function extraction

Published:2015-06-07 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 52nd Annual Design Automation Conference
language:
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Author:

Ciesielski Maciej¹,Yu Cunxi¹,Brown Walter¹,Liu Duo¹,Rossi André²

Affiliation:

1. University of Massachusetts, Amherst

2. Université de Bretagne-Sud - Lab STICC, France

Funder

National Science Foundation

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/2744769.2744925

Reference25 articles.

1. Replacing Testing with Formal Verification in Intel $^{\scriptsize\circledR}$ CoreTM i7 Processor Execution Engine Validation

2. Verification of arithmetic circuits with binary moment diagrams

3. Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs

4. M. Soos "Enhanced Gaussian Elimination in DPLL-based SAT Solvers " in Pragmatics of SAT Edinborough July 2010. M. Soos "Enhanced Gaussian Elimination in DPLL-based SAT Solvers " in Pragmatics of SAT Edinborough July 2010.

5. Functional vector generation for HDL models using linear programming and 3-satisfiability

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