Polynomial Formal Verification of Complex Circuits Using a Hybrid Proof Engine
Author:
Publisher
Springer Nature Switzerland
Link
https://link.springer.com/content/pdf/10.1007/978-3-031-40132-9_19
Reference26 articles.
1. Barhoush, M., Mahzoon, A., Drechsler, R.: Polynomial word-level verification of arithmetic circuits. In: ACM and IEEE International Conference on Formal Methods and Models for Codesign, pp. 1–9 (2021)
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3. Bryant, R.E.: On the complexity of VLSI implementations and graph representations of Boolean functions with application to integer multiplication. IEEE Trans. Comput. 40(2), 205–213 (1991)
4. Bryant, R.E., Chen, Y.A.: Verification of arithmetic circuits with binary moment diagrams. In: Design Automation Conference, pp. 535–541 (1995)
5. Burch, J.: Using BDDs to verify multipliers. In: Design Automation Conference, pp. 408–412 (1991)
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