Polynomial word-level verification of arithmetic circuits-Reference-Cited by-同舟云学术

Polynomial word-level verification of arithmetic circuits

Published:2021-11-20 Issue: Volume: Page:
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Container-title:Proceedings of the 19th ACM-IEEE International Conference on Formal Methods and Models for System Design
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Author:

Barhoush Mohammed¹,Mahzoon Alireza¹,Drechsler Rolf¹

Affiliation:

1. University of Bremen, Bremen, Germany

Funder

Deutsche Forschungsgemeinschaft

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3487212.3487333

Reference28 articles.

1. 2018. ABC: A System for Sequential Synthesis and Verification. available at https://people.eecs.berkeley.edu/~alanmi/abc/. 2018. ABC: A System for Sequential Synthesis and Verification. available at https://people.eecs.berkeley.edu/~alanmi/abc/.

2. Binary decision diagrams and beyond: enabling technologies for formal verification

3. David John Dempster and Michael George Stuart. 2001. Verification Methodology Manual - Techniques for Verifying HDL Designs. Teamwork International. David John Dempster and Michael George Stuart. 2001. Verification Methodology Manual - Techniques for Verifying HDL Designs. Teamwork International.

4. Combinational Equivalence Checking Using Incremental SAT Solving, Output Ordering, and Resets

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