Wrapping Paths of Undetected Transition Faults With Two-Cycle Gate-Exhaustive Faults
Author:
Affiliation:
1. School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA
Funder
Semiconductor Research Corporation
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software
Link
http://xplorestaging.ieee.org/ielx7/43/9956950/09721419.pdf?arnumber=9721419
Reference26 articles.
1. Gate exhaustive testing;cho;Proc IEEE Int Test Conf,2005
2. Evaluation of test metrics: Stuck-at, bridge coverage estimate and gate exhaustive;guo;Proc VLSI Test Symp,2006
3. The Region-Exhaustive Fault Model
4. Iterative Test Generation for Gate-Exhaustive Faults to Cover the Sites of Undetectable Target Faults
5. Maximal Independent Fault Set for Gate-Exhaustive Faults
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