1. A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-03
2. Diagnostic Test Point Insertion and Test Compaction;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-02
3. Topping Off Test Sets Under Bounded Transparent Scan;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-01
4. Wrapping Paths of Undetected Transition Faults With Two-Cycle Gate-Exhaustive Faults;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2022-12
5. Increasing the Fault Coverage of a Truncated Test Set;ACM Transactions on Design Automation of Electronic Systems;2022-06-27