Pole-Aware Analog Layout Synthesis Considering Monotonic Current Flows and Wire Crossings-Reference-Cited by-同舟云学术

Pole-Aware Analog Layout Synthesis Considering Monotonic Current Flows and Wire Crossings

Published:2023-01 Issue:1 Volume:42 Page:266-279
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Patyal Abhishek¹^ORCID,Chen Hung-Ming²^ORCID,Lin Mark Po-Hung²,Fang Guan-Qi³,Chen Simon Yi-Hung³

Affiliation:

1. Systems Design Group (SDG), Synopsys Taiwan Company Ltd., Hsinchu, Taiwan

2. Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan

3. Analog Design and Circuit Technology (ADCT), MediaTek Inc., Hsinchu, Taiwan

Funder

Taiwan MOST

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

Reference19 articles.

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