VirtualSync+: Timing Optimization With Virtual Synchronization-Reference-Cited by-同舟云学术

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VirtualSync+: Timing Optimization With Virtual Synchronization

Published:2022-12 Issue:12 Volume:41 Page:5526-5540
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Zhang Grace Li¹^ORCID,Li Bing¹^ORCID,Huang Xing¹^ORCID,Yin Xunzhao²^ORCID,Zhuo Cheng²^ORCID,Hashimoto Masanori³^ORCID,Schlichtmann Ulf¹^ORCID

Affiliation:

1. Chair of Electronic Design Automation, Technical University of Munich, Munich, Germany

2. College of Information Science and Electronic Engineering, Zhejiang University, Hangzhou, China

3. Graduate School of Informatics, Kyoto University, Kyoto, Japan

Funder

Deutsche Forschungsgemeinschaft

TRR 89 Invasive Computing

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx7/43/9956950/09718551.pdf?arnumber=9718551

Reference26 articles.

1. An efficient retiming algorithm under setup and hold constraints

2. Scalable min-register retiming under timing and initializability constraints

3. Retiming of Two-Phase Latch-Based Resilient Circuits

4. Incremental retiming for FPGA physical synthesis

5. Converting flip-flop to clock-gated 3-phase latch-based designs using graph-based retiming;cheng;IEEE Trans Comput -Aided Design Integr Circuits Syst,2021

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