Author:
Hurst Aaron P.,Mishchenko Alan,Brayton Robert K.
Cited by
4 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Trubol: Synthesis of Pipelined Circuits from Python-based DSL Specifications;2023 5th International Conference on Control Systems, Mathematical Modeling, Automation and Energy Efficiency (SUMMA);2023-11-08
2. VirtualSync+: Timing Optimization With Virtual Synchronization;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2022-12
3. Virtualsync;Proceedings of the 55th Annual Design Automation Conference;2018-06-24
4. Incremental min-period retiming algorithm for FPGA synthesis based on influence of fan-outs;Transactions of Tianjin University;2012-08