Areal Geometric Effects of a ZnO Charge-Trap Layer on Memory Transistor Operations for Embedded-Memory Circuit Applications
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/55/8015200/07986984.pdf?arnumber=7986984
Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Device Feasibility of 60-nm-Scaled Vertical-Channel Memory Transistors Using InGaZnO Channel and ZnO Charge-Trap Layers;IEEE Transactions on Electron Devices;2024-03
2. Transparent Structures for ZnO Thin Film Paper Transistors Fabricated by Pulsed Electron Beam Deposition;Micromachines;2024-02-12
3. Charge-trap memory effect in spray deposited ZnO-based electrolyte-gated transistors operating at low voltage;Current Applied Physics;2023-09
4. Synergic Impacts of CF4 Plasma Treatment and Post-thermal Annealing on the Nonvolatile Memory Performance of Charge-Trap-Assisted Memory Thin-Film Transistors Using Al–HfO2 Charge Trap and In–Ga–Zn–O Active Channel Layers;ACS Applied Electronic Materials;2022-03-07
5. Charge Trapping Augmented Switchable Sub-band-gap Photoresponse of Zinc–Tin Oxide Thin-Film Transistor;ACS Applied Electronic Materials;2020-06-22
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