A 9-bit 500-MS/s 6.0-mW dynamic pipelined ADC using time-domain linearized dynamic amplifiers
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/7833314/7844119/07844136.pdf?arnumber=7844136
Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A Large-Swing High-Linearity Fully-Dynamic Amplifier With Automatic Calibration;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-02
2. A 9-Bit 500-ms/s 4-Stage Pipelined SAR ADC With Wide Input Common-Mode Range Using Replica-Biased Dynamic Residue Amplifiers;IEEE Access;2023
3. A 1.55-mW 2-GHz ERBW 7-b 800-MS/s Pipelined SAR ADC in 28-nm CMOS Using a 7T Dynamic Residue Amplifier;IEEE Solid-State Circuits Letters;2022
4. 1.55mW 2GHz ERBW 7b 800MS/s 3-stage Pipelined SAR ADC in 28nm CMOS using a Kickback-Cancelling 7T-Dynamic Residue Amplifier with only 16fF Input Capacitance;2021 IEEE Asian Solid-State Circuits Conference (A-SSCC);2021-11-07
5. An 8.1 ENOB 10bit 400MS/s Pipelined ADC Using SAR and Sub-Ranging Flash;2021 IEEE International Symposium on Circuits and Systems (ISCAS);2021-05
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