A Large-Swing High-Linearity Fully-Dynamic Amplifier With Automatic Calibration
Author:
Affiliation:
1. School of Electronic Science and Engineering, University of Electronic Science and Technology of China, Chengdu, China
Funder
National Natural Science Foundation of China
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/10032206/09758068.pdf?arnumber=9758068
Reference11 articles.
1. A robust fully-dynamic residue amplifier for two-stage SAR assisted pipeline ADCs
2. A 9-bit 500-MS/s 6.0-mW dynamic pipelined ADC using time-domain linearized dynamic amplifiers
3. An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers
4. A Non-Interleaved 12-b 330-MS/s Pipelined-SAR ADC With PVT-Stabilized Dynamic Amplifier Achieving Sub-1-dB SNDR Variation
5. A 1.5 mW 68 dB SNDR 80 Ms/s 2 $\times$ Interleaved Pipelined SAR ADC in 28 nm CMOS
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