A Non-Interleaved 12-b 330-MS/s Pipelined-SAR ADC With PVT-Stabilized Dynamic Amplifier Achieving Sub-1-dB SNDR Variation-Reference-Cited by-同舟云学术

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A Non-Interleaved 12-b 330-MS/s Pipelined-SAR ADC With PVT-Stabilized Dynamic Amplifier Achieving Sub-1-dB SNDR Variation

Published:2017-12 Issue:12 Volume:52 Page:3235-3247
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Huang Hai^ORCID,Xu Hongda^ORCID,Elies Brian,Chiu Yun

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/8118328/08016325.pdf?arnumber=8016325

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2. SAR-MemPipe: A Hybrid Pipeline-SAR Memristive ADC for Analog Resistive Arrays;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

3. A 12-bit 1.5-GS/s Single-Channel Pipelined SAR ADC With a Pipelined Residue Amplification Stage;IEEE Journal of Solid-State Circuits;2024

4. An 8-bit 1.5-GS/s Two-Step SAR ADC With Embedded Interstage Gain;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-11

5. An improved PVT-Robust floating inverter dynamic amplifier for noise-shaping SAR ADCs;AEU - International Journal of Electronics and Communications;2023-10

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