An Enhanced Built-off-Test Transceiver with Wide-range, Self-calibration Engine for 3.2 Gb/s/pin DDR4 SDRAM-Reference-Cited by-同舟云学术

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An Enhanced Built-off-Test Transceiver with Wide-range, Self-calibration Engine for 3.2 Gb/s/pin DDR4 SDRAM

Published:2018-11 Issue: Volume: Page:
ISSN:
Container-title:2018 IEEE Asian Solid-State Circuits Conference (A-SSCC)
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Author:

Moon Joung-Wook,Yoo Hye-Sung,Choi Hundai,Park Il-Won,Kang Seok-Yong,Kim Jun-Bae,Chung Haeyoung,Kim Kiho,Lee Dong-Hun,Song Ki-Jae,Hyun Seok-Hun,Song Indal,Sohn Young-Soo,Cho Yong-Ho,Choi Jung-Hwan,Park Kwang-Il,Jang Seong-Jin

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8547238/8579249/08579329.pdf?arnumber=8579329

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Cost-Effective and Compact All-Digital Dual-Loop Jitter Attenuator for Built-Off-Test Applications;Electronics;2022-11-07

2. A 10Gb/s/pin DQS and WCK Built-Out Tester for LPDDR5 DRAM Test;2022 IEEE Asian Solid-State Circuits Conference (A-SSCC);2022-11-06

3. Generating Representative Test Sequences from Real Workload for Minimizing DRAM Verification Overhead;ACM Transactions on Design Automation of Electronic Systems;2020-09-02

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