The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips

Author:

Davidson Scott,Xie Shaolin,Torng Christopher,Al-Hawai Khalid,Rovinski Austin,Ajayi Tutu,Vega Luis,Zhao Chun,Zhao Ritchie,Dai Steve,Amarnath Aporva,Veluri Bandhav,Gao Paul,Rao Anuj,Liu Gai,Gupta Rajesh K.,Zhang Zhiru,Dreslinski Ronald,Batten Christopher,Taylor Michael Bedford

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 58 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Enabling Efficient Hybrid Systolic Computation in Shared-L1-Memory Manycore Clusters;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-09

2. Scalable, Programmable and Dense: The HammerBlade Open-Source RISC-V Manycore;2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA);2024-06-29

3. MuchiSim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems;2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS);2024-05-05

4. PAIR: Periodically Alternate the Identity of Routers to Ensure Deadlock Freedom in NoC;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22

5. MemPool: A Scalable Manycore Architecture With a Low-Latency Shared L1 Memory;IEEE Transactions on Computers;2023-12

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