Process Optimizations for Ge-On-Si Depletion Mode Transistors Using Mesa Architecture
Author:
Affiliation:
1. School of Computing and Electrical Engineering. Indian Institute of Technology, Mandi,Mandi,India
2. Institute of Semiconductor Engineering University of Stuttgart,Stuttgart,Germany
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10026850/10026886/10027013.pdf?arnumber=10027013
Reference15 articles.
1. Ohmic contacts to n-type germanium with low specific contact resistivity
2. Isotope Tracing Study of GeO Desorption Mechanism from GeO2/Ge Stack Using73Ge and18O
3. A Simplified Method for (Circular) Transmission Line Model Simulation and Ultralow Contact Resistivity Extraction
4. A Steep Slope MBE-Grown Thin p-Ge Channel FETs on Bulk Ge-on-Si Using HZO Internal Voltage Amplification
5. Radiation-Sensitive Novel Polymeric Resist Materials: Iterative Synthesis and Their EUV Fragmentation Studies
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Low-Temperature Processed Ni/GeSn Optimal Contacts for Junctionless GeSn-on-Si FinFETs;IEEE Transactions on Electron Devices;2024-09
2. Novel process integration flow of germanium-on-silicon FinFETs for low-power technologies;Journal of Vacuum Science & Technology B;2023-08-21
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