Novel process integration flow of germanium-on-silicon FinFETs for low-power technologies

Abstract

Germanium channel FinFET transistors process integration on a silicon substrate is a promising candidate to extend the complementary metal–oxide–semiconductor semiconductor roadmap. This process has utilized the legacy of state-of-art silicon fabrication process technology and can be an immediate solution to integrate beyond Si channel materials over standard Si wafers. The fabrication of such devices involves several complicated technological steps, such as strain-free epi layers over the Si substrate to limit the substrate leakage and patterning of narrow and sharp fins over germanium (Ge). To overcome these issues, the active p-type germanium layers were grown over n-type germanium and virtual substrates. The poly ((4-(methacryloyloxy) phenyl) dimethyl sulfoniumtriflate) was utilized as a polymeric negative tone e-beam resist for sub-20 nm critical dimensions with low line edge roughness, line width roughness, and high etch resistance to pattern p-Ge fins to meet these concerns. Here, the devices use the mesa architecture that will allow low bandgap materials only at the active regions and raised fins to reduce the active area interaction with the substrate to suppress leakage currents. This paper discusses the simple five-layer process flow to fabricate FinFET devices with critical optimizations like resist prerequisite optimization conditions before exposure, alignment of various layers by electron beam alignment, pattern transfer optimizations using reactive ion etching, and bilayer resist for desired lift-off. The Ge-on-Si FinFET devices are fabricated with a width and gate length of 15/90 nm, respectively. The devices exhibit the improved ION/IOFF in order of ∼105, transconductance Gm ∼86 μS/μm, and subthreshold slope close to ∼90 mV/dec.