Ge0.95Sn0.05 Gate-All-Around p-Channel Metal-Oxide-Semiconductor Field-Effect Transistors with Sub-3 nm Nanowire Width-Reference-Cited by-同舟云学术

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Ge0.95Sn0.05 Gate-All-Around p-Channel Metal-Oxide-Semiconductor Field-Effect Transistors with Sub-3 nm Nanowire Width

Published:2021-06-09 Issue:13 Volume:21 Page:5555-5563
ISSN:1530-6984
Container-title:Nano Letters
language:en
Short-container-title:Nano Lett.

Author:

Kang Yuye¹^ORCID,Xu Shengqiang¹,Han Kaizhen¹,Kong Eugene Y.-J.¹,Song Zhigang²³,Luo Sheng¹,Kumar Annie¹,Wang Chengkuan¹,Fan Weijun²,Liang Gengchiau¹,Gong Xiao¹^ORCID

Affiliation:

1. Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576, Singapore

2. School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, Singapore

3. State Key Laboratory of Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, P.O. Box 912, Beijing 100083, People’s Republic of China

Funder

Ministry of Education - Singapore

National Research Foundation Singapore

Publisher

American Chemical Society (ACS)

Subject

Mechanical Engineering,Condensed Matter Physics,General Materials Science,General Chemistry,Bioengineering

Link

https://pubs.acs.org/doi/pdf/10.1021/acs.nanolett.1c00934

Reference54 articles.

1. CMOS Scaling Trends and Beyond

2. International Roadmap for Devices and Systems (IRDS). IEEE, 2020. https://irds.ieee.org/editions/2020.

3. Mistry, K.; Allen, C.; Auth, C.; Beattie, B.; Bergstrom, D.; Bost, M.; Brazier, M.; Buehler, M.; Cappellani, A.; Chau, R.; A 45 nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193 nm Dry Patterning, and 100% Pb-free Packaging. In IEEE International Electron Devices Meeting (IEDM);Dec 10–12, 2007; IEEE: Piscataway, NJ, pp 247–250.

4. Natarajan, S.; Armstrong, M.; Bost, M.; Brain, R.; Brazier, M.; Chang, C.H.; Chikarmane, V.; Childs, M.; Deshpande, H.; Dev, K.; A 32 nm Logic Technology Featuring 2nd-Generation High-k + Metal-Gate Transistors, Enhanced Channel Strain and 0.171 μm2 SRAM Cell Size in a 291 Mb Array. In IEEE International Electron Devices Meeting (IEDM);Dec 15–17, 2008; IEEE: Piscataway, NJ, 2008; pp 941–943.

5. Auth, C.; Allen, C.; Blattner, A.; Bergstrom, D.; Brazier, M.; Bost, M.; Buehler, M.; Chikarmane, V.; Ghani, T.; Glassman, T.; A 22 nm High Performance and Low-Power CMOS Technology Featuring Fully-Depleted Tri-Gate Transistors, Self-Aligned Contacts and High Density MIM Capacitors. In IEEE Symposium on VLSI Technology;June 12–14, 2012; IEEE: Piscataway, NJ, 2012; pp 131–132.

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