A 2Mbit Digital in-Memory Computing Matrix-Vector Multiplier for DNN Inference supporting flexible bit precision and matrix size achieving 612 binary TOPS/W-Reference-Cited by-同舟云学术

A 2Mbit Digital in-Memory Computing Matrix-Vector Multiplier for DNN Inference supporting flexible bit precision and matrix size achieving 612 binary TOPS/W

Published:2023-09-11 Issue: Volume: Page:
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Container-title:ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC)
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Author:

Gupta Mohit¹,Cosemans Stefan¹,Debacker Peter²,Dehaene Wim³

Affiliation:

1. Axelera AI,Belgium

2. imec,Belgium

3. KU Leuven,Belgium

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10268677/10268683/10268763.pdf?arnumber=10268763

Reference18 articles.

1. Impact of Analog Non-Idealities on the Design Space of 6T-SRAM Current-Domain Dot-Product Operators for In-Memory Computing

2. A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS

3. Conv-RAM: An energy-efficient SRAM with embedded convolution computation for low-power CNN-based machine learning applications

4. A 64-Tile 2.4-Mb In-Memory-Computing CNN Accelerator Employing Charge-Domain Compute

5. 16.4 An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications;chih;2021 IEEE Int Solid-State Circuits Conf (ISSCC),2021

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