A 13.2fJ/step 74.3-dB SNDR Pipelined Noise-shaping SAR+VCO ADC
Author:
Affiliation:
1. Arizona State University,School of Elecmcal, Computer and Energy Engineering,AZ,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10268677/10268683/10268692.pdf?arnumber=10268692
Reference8 articles.
1. An 80dB-SNDR 98dB-SFDR Noise-Shaping SAR ADC with Duty-Cycled Amplifier and Digital-Predicted Mismatch Error Shaping
2. A First-Order Continuous-Time Noise-Shaping SAR ADC with Duty-Cycled Integrator
3. A 13.5-ENOB, 107?W noise-shaping SAR ADC with PVT-robust closed-loop dynamic amplifier;tang;IEEE JSSC,2020
4. An 84dB-SNDR Low-OSR 4th-Order Noise-Shaping SAR with an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique
5. A 600mV PP-Input-Range 94.5 dB-SNDR NS-SAR-Nested DSM with 4th-Order Truncation-Error Shaping and Input-Impedance Boosting for Biosignal Acquisition;jeong;IEEE Symposium on VLSI Circuits,2022
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