An 84dB-SNDR Low-OSR 4th-Order Noise-Shaping SAR with an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique
Author:
Affiliation:
1. Georgia Institute of Technology,Atlanta,GA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9731529/9731102/09731771.pdf?arnumber=9731771
Reference6 articles.
1. 27.3 A 13.8-ENOB 0.4pF-CIN 3rd-Order Noise-Shaping SAR in a Single-Amplifier EF-CIFF Structure with Fully Dynamic Hardware-Reusing kT/C Noise Cancelation
2. A 2MHz BW Buffer-Embedded Noise-Shaping SAR ADC Achieving 73.8dB SNDR and 87.3dB SFDR
3. 15.7 14b 35MS/S SAR ADC achieving 75dB SNDR and 99dB SFDR with loop-embedded input buffer in 40nm CMOS
4. A 13-ENOB 2nd-order noise-shaping SAR ADC realizing optimized NTF zeros using an error-feedback structure
5. 27.1 A 250kHz-BW 93dB-SNDR 4th-Order Noise-Shaping SAR Using Capacitor Stacking and Dynamic Buffering
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2. A Review on Fundamentals of Noise-Shaping SAR ADCs and Design Considerations;Chips;2024-05-10
3. A 93.6dB-SNDR 5kHz-BW Fully Dynamic Hybrid CT-DT Noise Shaping SAR ADC;2024 IEEE Custom Integrated Circuits Conference (CICC);2024-04-21
4. Energy Efficient ADC Design Techniques;2024 IEEE Custom Integrated Circuits Conference (CICC);2024-04-21
5. A 13.2fJ/step 74.3-dB SNDR Pipelined Noise-shaping SAR+VCO ADC;ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC);2023-09-11
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