A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM
Author:
Affiliation:
1. Institute of Semiconductors, Chinese Academy of Sciences,State Key Laboratory of Superlattices and Microstructures,Beijing,China
2. University of Macau,Macau,China
Funder
National Natural Science Foundation of China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10268677/10268683/10268691.pdf?arnumber=10268691
Reference9 articles.
1. A 3.3-4.5GHz Fractional-N Sampling PLL with A Merged Constant Slope DTC and Sampling PD in 40nm CMOS
2. A 2.4-GHz RF Fractional- ${N}$ Synthesizer With BW $= 0.25f_{\mathrm{ REF}}$
3. A 0.9–2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique
4. A-58 dBc-Worst-Fractional-Spur and -234 dBFoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a NonlinearityRobust DTC-Control Word;seong;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2020
5. A 4GHz 0.73ps _rms -Integrated-Jitter PVT-Insensitive Fractional-N Sub-Sampling Ring PLL with a Jitter-Tracking DLLAssisted DTC;jung;Proc Symp VLSI Circuits,2020
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