A 0.9–2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique-Reference-Cited by-同舟云学术

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A 0.9–2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique

Published:2018-05 Issue:5 Volume:26 Page:933-944
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Zhang Zhao^ORCID,Yang Jincheng,Liu Liyuan,Feng Peng,Liu Jian,Wu Nanjian^ORCID

Funder

National Natural Science Foundation of China

National Science and Technology Major Projects of the Ministry Science and Technology of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/8345376/08288673.pdf?arnumber=8288673

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