A 3.3-4.5GHz Fractional-N Sampling PLL with A Merged Constant Slope DTC and Sampling PD in 40nm CMOS-Reference-Cited by-同舟云学术

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A 3.3-4.5GHz Fractional-N Sampling PLL with A Merged Constant Slope DTC and Sampling PD in 40nm CMOS

Published:2021-06-07 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
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Author:

Jin Gaofeng,Feng Fei,Gao Xiang,Chen Wen,Shu Yiyang,Luo Xun

Funder

National Natural Science Foundation of China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9489353/9490399/09490495.pdf?arnumber=9490495

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 21.8–41.6-GHz Low Jitter and High FoMj Fast-Locking Subsampling PLL With Dead Zone Automatic Controller;IEEE Transactions on Microwave Theory and Techniques;2024-09

2. A Fractional-N Sampling PLL With a Merged Constant-Slope DTC and Sampling PD;IEEE Journal of Solid-State Circuits;2024-08

3. A high-pass shaped LMS algorithm based predistortion technique for fractional-N BB-DPLLs;Microelectronics Journal;2024-04

4. Fast locking Sampling PLL Using Phase Error Eliminator;2023 IEEE 15th International Conference on ASIC (ASICON);2023-10-24

5. A (0.75–1.13) mW and (2.4–5.2) ps RMS Jitter Integer-N-Based Dual-Loop PLL for Indoor and Outdoor Positioning in 28-nm FD-SOI CMOS Technology;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-10

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