Low-Power Approximate Adder Architecture for Image Processing Applications
Author:
Affiliation:
1. B V Raju Institute of Technology,ECE Department,Narsapur,Telangana
2. BVRIT,ECE Department,Narsapur,Telangana
3. GRIET,ECE Department,Hyderabad,Telangana
4. BITS Pilani Hyderabad Campus,EEE Department,Hyderabad,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10127223/10127224/10127377.pdf?arnumber=10127377
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5. Bio-inspired imprecise computational blocks for efficient VLSI implementation of soft-computing applications;mahdiani;IEEE Transactions on Circuits and Systems I Regular Papers,2009
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