Impacts of Clock Constraints on Side-Channel Leakage of HLS-designed AES Circuits-Reference-Cited by-同舟云学术

Impacts of Clock Constraints on Side-Channel Leakage of HLS-designed AES Circuits

Published:2023-02-05 Issue: Volume: Page:
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Container-title:2023 International Conference on Electronics, Information, and Communication (ICEIC)
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Author:

Miura Yuto¹,Mizuno Takumi¹,Nishikawa Hiroki²,Kong Xiangbo¹,Tomiyama Hiroyuki¹

Affiliation:

1. Ritsumeikan University,Graduate School of Science and Engineering,Shiga,Japan

2. Osaka University,Graduate School of Information Science and Technology,Osaka,Japan

Publisher

IEEE

Link

Reference7 articles.

3. A toolkit for power behavior analysis of HLS-designed FPGA circuits;zhang;Symposium on Low-Power and High-Speed Chips and Systems,2021

4. A testing methodology for side-channel resistance validation;goodwill;NIST Non-invasive Attack Testing Workshop,2011

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1. Impacts of Clock Frequency and Sampling Intervals on Power Side-Channel Leakage of AES Circuits;2024 International Conference on Electronics, Information, and Communication (ICEIC);2024-01-28

2. Simulation-based Analysis of Power Side-Channel Leakage at Different Sampling Intervals;2023 Eleventh International Symposium on Computing and Networking Workshops (CANDARW);2023-11-27