Simulation-based Analysis of Power Side-Channel Leakage at Different Sampling Intervals-Reference-Cited by-同舟云学术

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Simulation-based Analysis of Power Side-Channel Leakage at Different Sampling Intervals

Published:2023-11-27 Issue: Volume: Page:364-365
ISSN:
Container-title:2023 Eleventh International Symposium on Computing and Networking Workshops (CANDARW)
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Author:

Miura Yuto¹,Nishikawa Hiroki²,Kong Xiangbo³,Tomiyama Hiroyuki¹

Affiliation:

1. Ritsumeikan University,Graduate School of Science and Engineering,Shiga,Japan

2. Osaka University,Graduate School of Information Science and Technology,Osaka,Japan

3. Toyama Prefectural University,Graduate School of Faculty of Engineering,Toyama,Japan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10409776/10409777/10409782.pdf?arnumber=10409782

Reference8 articles.

1. A Survey on IoT Security: Application Areas, Security Threats, and Solution Architectures

2. An Inside Job: Remote Power Analysis Attacks on FPGAs

3. Impacts of Clock Constraints on Side-Channel Leakage of HLS-designed AES Circuits

4. Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis

5. A toolkit for power behavior analysis of HLS-designed FPGA circuits;Zhang

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Impacts of Clock Frequency and Sampling Intervals on Power Side-Channel Leakage of AES Circuits;2024 International Conference on Electronics, Information, and Communication (ICEIC);2024-01-28

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