A Two-Dimensional Model for the Field-Plate Design of High-Voltage Transistor

Author:

Lee Jian-Hsing1ORCID,Liao Chih-Cherng1,Shih Ching-Kuei1,Nidhi Karuna2ORCID,Li Ching-Ho1,Chen Chun-Chih1,Kan Kai-Chuan1,Chen Ke-Horng3ORCID

Affiliation:

1. Vanguard International Semiconductor Corporation, Hsinchu, Taiwan

2. Richtek Technology, Zhubei City, Hsinchu, Taiwan

3. Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Reference16 articles.

1. Ideal RESURF Geometries

2. High performance 600 V smart power technology based on thin layer silicon-on-insulator

3. The investigation of field plate design in 500 V high voltage NLDMOS;liu;Physics of Condensed Matter,2015

4. Extended-p+ stepped gate LDMOS for improved performance;jagadesh;IEEE Trans Elec Dev,2010

5. A Study of LDMOS BV Improvement by Gate Architecture Optimization

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1. Automatic optimal design of field plate for silicon on insulator lateral double‐diffused metal oxide semiconductor using simulated annealing algorithm;IET Power Electronics;2024-02-12

2. RESURF Region Variation Induced Current Crowding Effect on HV p-LDMOS;2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA);2023-07-24

3. A Combination of Implant Shadow and Skin Effects Leading to HV Devices Failure during the ESD Event;2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA);2023-07-24

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