Analytical Model of CFET Parasitic Capacitance for Advanced Technology Nodes-Reference-Cited by-同舟云学术

Analytical Model of CFET Parasitic Capacitance for Advanced Technology Nodes

Published:2022-03 Issue:3 Volume:69 Page:936-941
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Sun Bingqi¹^ORCID,Xu Zhongshan²^ORCID,Ding Rongzheng¹^ORCID,Yang Jingwen¹,Chen Kun¹^ORCID,Xu Saisheng¹,Xu Min¹,Lu Ye¹^ORCID,Zhu Xiaona¹^ORCID,Yu Shaofeng¹^ORCID,Zhang David¹

Affiliation:

1. State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai, China

2. Shanghai Integrated Circuit Manufacturing Innovation Center Company Ltd., Shanghai, China

Funder

Shanghai Sailing Program

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/9722602/09704878.pdf?arnumber=9704878

Reference12 articles.

1. Electrostatics in free space;robert elliott;Electromagnetics History Theory and Applications,1993

2. First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications

3. Further study on electrostatic capacitance of an inclined plate capacitor

4. Fringe Capacitance Modeling in NanoPlate MOSFET Using Conformal Mapping

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